本文设计了一种通用的边界扫描时钟单元。
A general purpose JTAG Boundary-Scan Clock Cell is designed in this paper.
主控器设计是边界扫描测试系统设计的重点。
The design of a BSM is the key problem of the implementation of the Boundary Scanning Test System implementation.
逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
Some problems in logic cluster boundary scan test could not be neglected.
行移文本水印算法，强鲁棒性，边界扫描采用投影法。
Line shift text watermarking algorithm, strong robustness, use of boundary.
因此利用边界扫描结构来对系统进行调试的方法应运而生。
Therefore the method making use of boundary scan structure to carry out a debugging on system arises at the historic moment.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
边界扫描技术作为一种新兴的BIT技术，在工业界内得到了广泛的应用。
As a kind of new developing BIT technology, Boundary scan technology is widely used in industry.
并且目前各大公司生产的超大规模集成电路芯片基本全部具有边界扫描结构。
Grand scale IC chip that every important company produces at present is almost all having the boundary scan structure.
与边界扫描技术相比，本系统具有结构简单、操作时间短、性价比高的特点。
Compared with BST, the system has advantages of simple structure, short operation time, and cost-efficient.
该文简述了边界扫描基本协议，详细介绍了本系统的结构和工作原理及其算法。
This article gives a brief introduction to JTAG boundary scan basic protocol and describes in detail the structure, theory and algorithm of the system .
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
电子产品微型化使自动测试成为必然，而边界扫描技术则使自动测试成为可能。
The miniaturization of electronic products results in automatic testing, which is made possible by boundary scan technology.
本文详细介绍了边界扫描测试的原理、结构，讨论了边界扫描测试技术的应用。
The working principle and architecture of BST is introduced in this paper and its applications are discussed.
首次采用先进的边界扫描技术实现了以无打扰的方式完成CPU模块的故障检测。
The CPU module 's fault is detected in no - disturb way for the first time with the advanced boundary scan technology.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
采用DSP和边界扫描总线控制芯片74lvt8980设计边界扫描测试控制器。
A boundary scan controller with the USB interface is designed. DSP and 74lvt8980 are adopted to control the boundary scan bus.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
There are some common methods of design for testability, such as boundary scan test and so on.
介绍了数据采集的原理和ASIC的基本功能、实现以及JTAG的边界扫描测试技术。
In this paper, the principle of data collection, the basic function and implementation of asic and the technology of JTAG BST are presented.
本文介绍了开发的边界扫描测试仪样机的工作原理，并着重论述了其软件开发的几个重要问题。
In this paper, a boundary-scan prototype tester is introduced. Some problems in developing its software system are emphasized.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
本文在阐述边界扫描测试原理的基础上，重点讨论了所开发的一种用于边界扫描测试的虚拟仪器。
With the analysis of the boundary scanning principle, this paper discusses a virtual instrument for boundary scanning test.
本文还讨论了两种智能故障诊断技术，即专家系统智能故障诊断技术和边界扫描测试智能故障诊断技术。
The paper also discusses two intelligent fault diagnostic methods: expert system intelligent fault diagnostic method and boundary-scan technique intelligent fault diagnostic method.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
IEEE1149标准及其子标准是基于边界扫描的测试技术，它们针对不同的应用环境采用相应的技术标准。
IEEE1149 standard and its. X sub standards are based on boundary scan technique, different standards can be appropriately selected for various of applications.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
应用推荐