This has undesired effects on some GIC registers, for eg GICC_IAR register can only read once to acknowledge the interrupt.
这不希望一些GIC寄存器效果,如GICC_IAR寄存器只能读一次承认中断。
The analysis and experiments shows that an interrupt must take place during the halt acknowledge cycle of the CPU.
分析与实验结果表明,中断必须发生在CPU的暂停响应阶段。
The analysis and experiments shows that an interrupt must take place during the halt acknowledge cycle of the CPU.
分析与实验结果表明,中断必须发生在CPU的暂停响应阶段。
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