The SP505 also includes a latch enable pin with the driver and receiver address decoder.
SP505还包括一个带有驱动器和接收器地址译码器的锁存使能管脚。
This paper proposes a high speed and low power pulse latch design, and integrates it to high speed DSP address generator.
提出了一种高速低功耗脉冲寄存器的设计方法,并将其应用在高速DSP地址生成单元的设计中。
This paper proposes a high speed and low power pulse latch design, and integrates it to high speed DSP address generator.
提出了一种高速低功耗脉冲寄存器的设计方法,并将其应用在高速DSP地址生成单元的设计中。
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