This paper introduces a practic design version of all-digital PLL.
本文介绍一种实用的全数字锁相环方案。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
应用推荐