A design of high speed backplane bus is introduced in this paper.
介绍了一个高速背板总线的设计尝试。
This bridge is the core of communication of the controller system, it connects the bottom level backplane bus, backplane bus controller, and PC EPP parallel port.
该总线桥是某型协调控制器系统的通讯核心，实现了系统下层的背板总线、背板总线管理器与上位机epp并口之间的协议转换以及通讯仲裁功能。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
Especially in the bus design on the backplane, we should pay more attention to the distribution, interconnection of the clock, data line.
背板上的总线时钟和数据线的分布，互连设计显得尤为重要。
Especially in the bus design on the backplane, we should pay more attention to the distribution, interconnection of the clock, data line.
背板上的总线时钟和数据线的分布，互连设计显得尤为重要。
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