Built-in self-test (BIST) is used as an effective test technique and it can greatly reduce test overheads.

内建自测试(BIST)作为一种有效的测试技术可以大大地降低测试开销。

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To reduce the storage volume of the test data during the built-in self-test (BIST), a new BIST technique based on two dimensional compression of test data is presented.

为压缩内建自测试(BIST)期间所需测试数据存储容量，提出了一种新的基于测试数据两维压缩的BIST方案。

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For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.

针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。

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Aiming at the mixed-signal circuit testing, an integrated built-in self test (BIST) architecture for testing on-chip high speed ADC was presented.

针对混合信号电路的测试问题，提出了一种内建自测试(BIST)结构，分析并给出了如何利用该结构来计算片上高速模数转换器(adc)的静态参数。

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Aiming at the mixed-signal circuit testing, an integrated built-in self test (BIST) architecture for testing on-chip high speed ADC was presented.

针对混合信号电路的测试问题，提出了一种内建自测试(BIST)结构，分析并给出了如何利用该结构来计算片上高速模数转换器(adc)的静态参数。

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