A general purpose JTAG Boundary-Scan Clock Cell is designed in this paper.
本文设计了一种通用的边界扫描时钟单元。
In this paper, a boundary-scan prototype tester is introduced. Some problems in developing its software system are emphasized.
本文介绍了开发的边界扫描测试仪样机的工作原理，并着重论述了其软件开发的几个重要问题。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
Many in-circuit testers now have boundary-scan test capability. With boundary-scan testing, you can test interconnections on PCBs without using a probe on each node.
很多测试设备具有分界扫描的功能，这样，测试人员就可以直接测试印刷电路板上的互连，而没用必要使用探针去测试每一个节点了。
Joint test Action Group designed a common chip boundary-scan structure and test access port criterion which is called JTAG standard to support testing on-board chip or logic.
为支持板上芯片或逻辑的测试，联合测试行动小组专门设计和定义了一种通用的芯片边界扫描结构及其测试访问端口规范，称为JTAG标准。
This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability.
本文以usb逻辑分析仪作为一种典型的被测对象，进行了可测性设计的再开发工作，使其具有支持IEEE 1149.1边界扫描功能的设备结构。
The paper also discusses two intelligent fault diagnostic methods: expert system intelligent fault diagnostic method and boundary-scan technique intelligent fault diagnostic method.
本文还讨论了两种智能故障诊断技术，即专家系统智能故障诊断技术和边界扫描测试智能故障诊断技术。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法，弥补了传统测试的缺陷，为复杂的电路互连提供了测试手段。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
This paper discussed the application of boundary-scan technology to prototype board debugging and the problems of extension to volume board manufacturing, system integration, and field service.
本文讨论了边界扫描技术在样机电路板调试中的应用以及扩展到产品板制造、系统集成和现场服务等方面应用的技术问题。
The paper proposes applying boundary-scan technology which is widely used in the domain of test to the computer hardware experiment to resolve the two crucial problems of configuration and test.
本文提出将测试领域成熟的边界扫描技术应用在实验系统中，解决配置和验证两大关键问题。
On the basis of mixed-signal Boundary scan technology, a scheme of mixed-signal Boundary-scan test system is presented and the hardwares are implemented, including the controller and display unit.
基于混合信号边界扫描技术标准，提出混合信号边界扫描控制器的设计方案并实现了其硬件设计，包括边界扫描控制模块、显示驱动模块等。
Some problems in logic cluster boundary scan test could not be neglected.
逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
An unintended boundary condition arises when the scan circuitry is not disabled.
当扫描电路未被关闭的时候会出现预期之外的边界条件。
JTAG Boundary Scan is a new technique for connection test. With the help of JTAG, we can find out all connection faults of a complicated board or system.
JTAG边界扫描机制是用于在线导通测试的新技术，利用JTAG可以在数分钟内查出复杂插件和系统的全部导通故障。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
As a kind of new developing BIT technology, Boundary scan technology is widely used in industry.
边界扫描技术作为一种新兴的BIT技术，在工业界内得到了广泛的应用。
IEEE1149 standard and its. X sub standards are based on boundary scan technique, different standards can be appropriately selected for various of applications.
IEEE1149标准及其子标准是基于边界扫描的测试技术，它们针对不同的应用环境采用相应的技术标准。
This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
Scan technique and boundary scan technique are the main stream technology of current DFT technique. They can solve the internal testable problems and the connection problems between ICs respectively.
扫描技术和边界扫描技术是目前可测试性设计的主流技术，可分别用来解决芯片内部与芯片之间的可测试性问题。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
So the design of boundary scan is essential in the design of chips. IEEE instituted a standard for it, and the standard is IEEE1149.1 (that can be called as JTAG standard also).
边界扫描设计已逐渐成为芯片设计中不可或缺的部分，IEEE为其制定了相关标准，即ieee1149.1标准(也称为JTAG标准)。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
The miniaturization of electronic products results in automatic testing, which is made possible by boundary scan technology.
电子产品微型化使自动测试成为必然，而边界扫描技术则使自动测试成为可能。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
The BSDL language that describes boundary scan components is thoroughly studied, and then applied to boundary scan ATPG tools and fault diagnosis software.
在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试图形生成atpg与故障诊断软件中。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
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