Some problems in logic cluster boundary scan test could not be neglected.
逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
As a kind of new developing BIT technology, Boundary scan technology is widely used in industry.
边界扫描技术作为一种新兴的BIT技术，在工业界内得到了广泛的应用。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
The CPU module 's fault is detected in no - disturb way for the first time with the advanced boundary scan technology.
首次采用先进的边界扫描技术实现了以无打扰的方式完成CPU模块的故障检测。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Grand scale IC chip that every important company produces at present is almost all having the boundary scan structure.
并且目前各大公司生产的超大规模集成电路芯片基本全部具有边界扫描结构。
The miniaturization of electronic products results in automatic testing, which is made possible by boundary scan technology.
电子产品微型化使自动测试成为必然，而边界扫描技术则使自动测试成为可能。
Therefore the method making use of boundary scan structure to carry out a debugging on system arises at the historic moment.
因此利用边界扫描结构来对系统进行调试的方法应运而生。
A boundary scan controller with the USB interface is designed. DSP and 74lvt8980 are adopted to control the boundary scan bus.
采用DSP和边界扫描总线控制芯片74lvt8980设计边界扫描测试控制器。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
The automatic testing software which is compatible with BSDL files and EDIF files can complete multiple boundary scan test tasks.
兼容于BSDL和EDIF文件格式的自动测试向量生成软件可实现多种扫描测试功能。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
This article gives a brief introduction to JTAG boundary scan basic protocol and describes in detail the structure, theory and algorithm of the system .
该文简述了边界扫描基本协议，详细介绍了本系统的结构和工作原理及其算法。
JTAG Boundary Scan is a new technique for connection test. With the help of JTAG, we can find out all connection faults of a complicated board or system.
JTAG边界扫描机制是用于在线导通测试的新技术，利用JTAG可以在数分钟内查出复杂插件和系统的全部导通故障。
The BSDL language that describes boundary scan components is thoroughly studied, and then applied to boundary scan ATPG tools and fault diagnosis software.
在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试图形生成atpg与故障诊断软件中。
IEEE1149 standard and its. X sub standards are based on boundary scan technique, different standards can be appropriately selected for various of applications.
IEEE1149标准及其子标准是基于边界扫描的测试技术，它们针对不同的应用环境采用相应的技术标准。
In the end, the boundary scan test technology is introduced as the useful complement to functional self-test method, which can improve the fault isolation rate.
最后介绍了边缘扫描测试技术，指出边缘扫描测试技术是功能自测试方法的有益补充，能够有效提高测试的故障隔离率。
So the design of boundary scan is essential in the design of chips. IEEE instituted a standard for it, and the standard is IEEE1149.1 (that can be called as JTAG standard also).
边界扫描设计已逐渐成为芯片设计中不可或缺的部分，IEEE为其制定了相关标准，即ieee1149.1标准(也称为JTAG标准)。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu…
实际应用中，大多数器件没有边界扫描接口，因此本文所介绍的边界扫描技术实现方法对进行数字系统的可测性设计具有一定的参考价值。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
On the basis of mixed-signal Boundary scan technology, a scheme of mixed-signal Boundary-scan test system is presented and the hardwares are implemented, including the controller and display unit.
基于混合信号边界扫描技术标准，提出混合信号边界扫描控制器的设计方案并实现了其硬件设计，包括边界扫描控制模块、显示驱动模块等。
Two test methods, both test on boundary scan and test-by-divider, are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock.
分别给出了边界扫描测试和分频器测试两种测试方案，并对两种方案进行了比较，指出了各自的适用范围。
Scan technique and boundary scan technique are the main stream technology of current DFT technique. They can solve the internal testable problems and the connection problems between ICs respectively.
扫描技术和边界扫描技术是目前可测试性设计的主流技术，可分别用来解决芯片内部与芯片之间的可测试性问题。
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