A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.

针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。

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In this thesis, a high-speed, low-power and third-order current-mode charge-pump PLL is designed according to the CDMA standard by in-depth analyzing and researching the principle of PLL.

通过对锁相环原理进行深入的分析和研究，本论文针对CD MA无线通信标准，设计出了高速低功耗三阶电流型电荷泵锁相环。

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A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.

提出了一种全新的电荷泵锁相环的行为级建模方法。

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Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.

电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。

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Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.

电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。

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