Low-power oriented design techniques include selecting low-power parts, low operation voltage, managing clock of MCU or making MCU turn into dormancy, managing power supply of circuit and so on.
低功耗设计的关键技术包括选用低功耗的各类器件，低工作电压，对MCU进行时钟管理或休眠，对各部分电路和器件进行电源管理等。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
This commercial integrated chip can be used in the local oscillation circuit, high-accuracy clock generator and so on.
这种商用集成芯片可用于本振合成回路，高精度时钟发生器等。
The data acquisition system consists of the signal conditioning circuit, DSK interfacing circuit, RS-485 communication interfacing circuit, system clock circuit, the power circuit, and so on.
数据采集系统包括信号调理电路、DSK接口电路、RS- 485通信接口电路、系统时钟电路及电源电路等。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
This circuit is implemented on a monolithic chip, which is comprised of a period time sampling unit, a peri-od distanee preset unit, an arithmetic unit, a clock and time sequence unit.
电路主要由周期计时电路、周期数据预置电路、运算电路及时钟和时序等电路构成。
The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
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