A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.
大量的实验结果表明：与基于模拟器的方法相比，采用该系统可以快速综合出可制造的深亚微米cmos模拟单元电路。
This paper presented the various technologies in RF design and explored the feasibility and difficulties of deep sub micron CMOS RF design. And problems associated are also discussed.
本文介绍了当今RF设计的主流工艺，并分别对基于硅的深亚微米cmos工艺在RF设计中的可行性和困难进行了研究，评述了其中存在的问题。
A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper.
介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统。
A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper.
介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统。
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