In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
The thesis presents the design and realization of a data synchronous acquisition system in integrated protection based on FPGA and digital frequency multiplying technique.
本论文的任务是设计并实现基于FPGA及数字倍频技术的集成保护中数据同步采集系统。
Complex Programmable Logic Device (CPLD) is one of Application Specific Integrated Circuit (ASIC) that has been widely used, especially adapt to design digital system.
复杂可编程逻辑器件(CPLD)是目前应用最为广泛的可编程专用集成电路(ASIC)之一，特别适合于数字系统的设计和开发。
With the help of ti CCS3.1 integrated development environment, system software design USES ti own image processing library functions to complete fast digital image processing.
系统软件设计部分在TI公司CCS3.1集成开发环境下，运用TI公司自带图像处理库函数进行快速数字图像处理。
This design is integrated with MCU control all of the above FM function ASIC design of a digital FM radio system.
本设计就是用单片机控制集成了上述所有FM功能的专用芯片，设计一个数字FM收音机系统。
Under the support of net-work system, The platform integrated 3D digital design, computer-aided analysis and computer-aided process design function etc.
此平台具备网络系统支持下的设备三维数字化设计、计算机辅助分析、计算机辅助工艺设计、可视化及三维交互等功能。
Under the support of net-work system, The platform integrated 3D digital design, computer-aided analysis and computer-aided process design function etc.
此平台具备网络系统支持下的设备三维数字化设计、计算机辅助分析、计算机辅助工艺设计、可视化及三维交互等功能。
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