GFMS is a Gate and Function Block of mixed-level simulation system, which is designed for experiment of Digital Logical.
GFMS是针对《数字逻辑》课程实验而设计的数学电路模拟系统。
VHDL, however, can make effective description of the digital system and enable logical synthesis to produce high design density.
VHDL语言能方便地进行数字系统描述，而且能使逻辑综合产生更大的设计密度。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
It includes programming logical controller, digital direct current adjustable rate system, steel wick sticks crackle detect system, steel pipe track system.
整个系统由可编程控制器、全数字式直流调速系统、芯棒断裂检测系统、管料跟踪系统等构成。
Since the traditional hardware evolutionary methods based on logical gates were only valid to evolve simple digital circuits, a method of on-line system-level evolution was proposed.
现有基于逻辑门的底层硬件进化方法只能进化小规模数字电路，由此提出了一种硬件系统级在线进化方法。
Since the traditional hardware evolutionary methods based on logical gates were only valid to evolve simple digital circuits, a method of on-line system-level evolution was proposed.
现有基于逻辑门的底层硬件进化方法只能进化小规模数字电路，由此提出了一种硬件系统级在线进化方法。
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