The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
This paper deals with the design and realization of logic synthesis system from behavioural description to structure description developed by DA Lab. of Beijing Institute of Technology.
本文详述了北京理工大学DA实验室开发的从行为功能级描述到结构描述的自动综合系统的设计与实现。
The design includes system level design, RTL level design and logic synthesis.
设计工作包括系统级设计、RTL级设计、逻辑综合。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
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