Writing process is complete page-based virtual memory address translation process management and simulation page fault handling.
编写程序完成页式虚拟存储管理中地址转换过程和模拟缺页中断的处理。
TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.
tlb缓存条目重用(缓存命中)意味着更快的地址转换，还意味着对物理内存的更快的访问。
Pacifica also amends address translation with host and guest memory management unit (MMU) tables.
Pacifica还可以使用宿主和客户内存管理单元(MMU)表来进行地址转换。
To help address translation, operating systems cache the translated memory addresses by a process called Translation Look-aside Buffering (TLB).
为了帮助地址转换，操作系统通过一个叫做转换后援缓冲（Translation Look-aside Buffering，TLB） 的进程来缓存已转换的内存地址。
As mentioned before, memory addresses that are referred by a process are virtual addresses and require translation to the physical address.
如前所述，进程所引用的内存地址是虚拟地址，需要将其转换成物理地址。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
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