The processors 5, 10 May each include a local memory controller hub (MCH) 15, 20 to allow communication with memories 15, 20.
处理器5和10可各自包括允许与存储器15和20通信的存储器控制器集线器(MCH) 15和20。
The processors 5, 10 May each include a local memory controller hub (MCH) 15, 20 to allow communication with memories 15, 20.
处理器5和10可各自包括允许与存储器15和20通信的存储器控制器集线器(MCH) 15和20。
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