An important problem in multi-clock domain design is how to avoid metastability.
多时钟域设计的一个难题是如何避免亚稳态的产生。
Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个关键。
The design of asynchronous FIFO meets with two troubles, metastability and how to generate empty and full flag correctly.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个难题。
Using the proposed design techniques and optimization methods, metastability could be controlled and system reliability could be improved.
提供的设计技巧和优化手段在实践中可以很好地抑制亚稳态，提高系统可靠性。
Metastability failure may occur when a connection is needed between two asynchronous units, or a digital signal is sampled by another asynchronous system.
两个异步单元之间的联接、或是一个信号引入一与之异步的系统时，可能会引起亚稳态而导致故障。
Most of the ASIC" s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock do-main design is how to avoid metastability."
绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。
But solid explosives are high-energy metastability materials, when encountered external stimulation to the reactive threshold, a strong chemical reaction will occur.
固体炸药是一种蕴含高能量的亚稳态物质，遇外界刺激达到一定阈值就会发生强烈化学反应。
Generation mechanism of metastability was discussed, and metastability in FPGA design was analyzed. A number of effective solutions were presented to solve the problem of metastability.
探讨了亚稳态的产生机制，对FPGA设计中的亚稳态进行分析，针对FPGA设计中的亚稳态问题，给出了一系列行之有效的解决方法。
Generation mechanism of metastability was discussed, and metastability in FPGA design was analyzed. A number of effective solutions were presented to solve the problem of metastability.
探讨了亚稳态的产生机制，对FPGA设计中的亚稳态进行分析，针对FPGA设计中的亚稳态问题，给出了一系列行之有效的解决方法。
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