This paper presents a new method named "multilevel logic optimization for area" which aims at the area of the subject-graph.
该文针对主题图面积的优化问题，提出了“多级逻辑面积优化”设计方法。
The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper.
本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。
Multilevel optimization is implemented by a series of logic structural transformations which delete the redundant lines and gates to improve some local structures.
消除多级逻辑结构中冗余的逻辑连线、冗余逻辑门并进行相应的等价逻辑结构变换，实现多级逻辑优化。
Multilevel optimization is implemented by a series of logic structural transformations which delete the redundant lines and gates to improve some local structures.
消除多级逻辑结构中冗余的逻辑连线、冗余逻辑门并进行相应的等价逻辑结构变换，实现多级逻辑优化。
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