The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes.
文章提出的新型乘法累加器，具有在不同模式下分别处理16位与32位数据，或16位与32位数据混合运算能力。
The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes.
文章提出的新型乘法累加器，具有在不同模式下分别处理16位与32位数据，或16位与32位数据混合运算能力。
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