Output jitter is defined in three ways: period jitter. duty-cycle jitter, and phase jitter.
输出时钟抖动定义为三种类型：周期抖动，占空比抖动和相位抖动。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
This paper describes in detail the method to analyze the Phase jitter in the four-level PWM fibre optic communication systems.
本文详细介绍了四进制pwm光纤通信系统相位抖动的分析方法。
The effects of the sliding-frequency guiding filters on reducing soliton phase jitter were theoretically studied by perturbation theory.
采用微扰法，分析了滑频滤波器抑制孤子相位抖动。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
Phase-average network is a type of network which can carry out phase average for several pulses having phase jitter and achieves a kind of special paise signal.
相位平均网络是一种能把多个有相位抖动的脉冲进行相位平均，得到一种特殊脉冲信号的网络。
The paper analyzes the interference rejection of Quadrature amplitude modulation signals in the presence of carrier phase jitter, sinusoidal interference and white Gaussian noise.
文章分析了存在载波相位起伏、正弦干扰、高斯白噪声时正交调幅数字系统的抗扰性。
The paper introduce the concepts of timing parameters, including: jitter, phase noise, skew, frequency stabilization, and the relationship between them.
本文介绍了时钟网络中抖动、相位噪声、偏移、频率稳定度等参数的概念以及它们之间的转换关系。
The SSB phase noise and timing jitter are further analyzed in this experiment.
在这实验，相位杂讯和时序抖动被进一步做分析。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
Unique to the 5372A (compared with the 5371A) are deeper memory, hardware histograms, and FFT capabilities for high-performance and more sophisticated jitter spectrum analysis and phase noise studies.
独特的向5372a （相比，与5371a ）是更深的记忆体，硬体直方图，和FFT能力高的性能和更复杂的抖动频谱分析和相位噪声的研究。
Timing jitter induced by SPM and IXPM could be suppressed totally by adjusting the relative phase between the center frequency of the pulse and the ripples.
通过调整脉冲的中心频率与纹波之间的相位差将有可能完全抑制时间抖动。
As the voltage VCTR varies, VCO 104 varies the frequency of the VCO output signal, causing phase offsets and increased output jitter when PLL 100 is in lock mode, as shown by dotted line 202.
随着电压VCTR改变，VCO 104改变VCO输出信号的频率，使得当pll 100处于锁定模式时引起脉冲偏移和增大的输出抖动，如图中虚线202所示。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.
电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。
MT-008 Converting Oscillator Phase Noise to Time Jitter.
提供一种将相位噪声转化为时域抖动的方法。
MT-008 Converting Oscillator Phase Noise to Time Jitter.
提供一种将相位噪声转化为时域抖动的方法。
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