Portions of the oxide layer are removed to substantially planarize the trench-filled oxide layer as the first polysilicon layer.
所述氧化层的部分被移除，以使所述沟槽填充的氧化层作为第一多晶硅层基本平面化。
The first polysilicon layer also includes a void therein.
第一多晶硅层还包括在其中的空隙。
A transistor may be formed with a first polysilicon layer covered by a dielectric.
晶体管可以形成为具有被电介质覆盖的第一多晶硅层。
An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse.
杂质掺杂多晶硅层设置于两绝缘区与反熔丝上。
A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.
在衬底上形成第二多晶硅层，以便第二多晶硅层填充凹部。
Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening.
然后，在衬底上形成第一多晶硅层，以便第一多晶硅层填充开口。
An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed.
第一多晶硅层的上部被除去，以便空隙扩大到凹部，以及凹部被露出。
A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line.
多晶硅化金属层设置于杂质掺杂多晶硅层上，而多晶硅化金属层与多晶硅层可作为字线。
The bilayer cantilevers, formed with a polysilicon layer and a gold layer, elevate the mirror plate according to residual stress-induced bending.
支撑臂由多晶硅层和金层构成，在残余应力的作用下发生弯曲而将镜体提起。
Through a CMP process, portions of the oxide layer are removed to substantially planarize the trench-filled oxide layer as the first polysilicon layer.
利用一化学机械研磨制程，移除该氧化 物层的部分区域，以使该填满沟槽的氧化物层与该第一多晶硅层大体上齐平。
Finally, the second substrate covered with the second non-crystalline silicon layer is annealed with the laser with the second energy density to form the second polysilicon layer.
最后，以具有第二既定能量密度的激光对表面覆盖有一第二非晶硅层的第二衬底实施退火处理，以形成一第二多晶硅层。
The device utilizes three phase construction with the technology of buried channel and three layer polysilicon.
该器件为三相结构，采用埋沟和三层多晶硅技术。
The device utilizes three-phase construction, with the technology of buried-channel and four-layer polysilicon.
该器件采用三相结构，埋沟和四层多晶硅技术。
The device utilizes three-phase construction, with the technology of buried-channel and four-layer polysilicon.
该器件采用三相结构，埋沟和四层多晶硅技术。
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