Introduce to a 64-bit RISC microprocessor design.
文章介绍了一种64位RISC微处理器的结构设计。
The development of instruction level power model is discussed to our self-made LS-RISC microprocessor.
针对笔者自主研制的LS -RISC微处理器，讨论了其指令级功耗模型的开发。
RISC microprocessor is developed by using modular design method and VHDL language based on FPGA and EDA technology.
基于FPGA和电子设计自动化技术。采用模块化设计的方法和VHDL语言，设计一个基于FPGA的RISC微处理器。
This paper introduces the design of RISC microprocessor with pipelining based on FPGA, which is included the design of key modules and pipelining.
文章介绍了基于FPGA的流水线RISC微处理器的设计，包括关键模块设计和流水线设计。
According to that, a 32bit configurable media-enhanced RISC microprocessor RISC32 (RISC3201 and RISC3202) is designed for media processing and system controlling.
为此，结合嵌入式多媒体信号处理与系统控制特点而设计了32位可配置媒体增强RISC微处理器核RISC32（包括RISC3201和RISC3202）。
According to three aspects: data types, instruction formats, and instruction set, the architecture of an embedded 32 bit RISC microprocessor is introduced in this paper.
本文从数据类型、指令格式与指令集合三个方面介绍一种嵌入式32位RISC微计算机的体系结构。
According to three aspects: data types, instruction formats, and instruction set, the architecture of an embedded 32 bit RISC microprocessor is introduced in this paper.
本文从数据类型、指令格式与指令集合三个方面介绍一种嵌入式32位RISC微计算机的体系结构。
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