Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
The second is where you have to integrate the loop closely with the sequential logic.
第二点是，人们必须将一些控制环与顺序逻辑控制更紧密地集成。
For sequential logic, the key is clock. Everything has to be synchronized with clock.
之前看的那些顺序逻辑的例子好像确实全都没有时钟信号。
This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.
时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。
It is demonstrated that the SRL can be used for both combinatorial and sequential logic functions, and as all-optical regeneration devices.
SRL不但可用来实现组合的和顺序的逻辑功能，还可用于全光再生器件。
The principle of using sequential logic circuit and 8031 monolithic computer for realizing continuous pulse duration measure are introduced.
主要介绍了用时序逻辑电路实现连续脉冲宽度测量的工作原理，并讨论了采用8031单片机的实现方案。
This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.
本文给出一个时序逻辑电路的多故障测试模拟程序。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
This paper has discussed the logic behaviour of flip-flops using the four valued logic and its applications in the analysis and design of pulsed asynchronous sequential logical networks.
本文利用四值逻辑讨论了触发器的逻辑功能，并讨论四值逻辑在脉冲异步时序逻辑网络分析和设计中的应用。
In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
PLC programming technique includes experience design method, logic design method, cycle diagram design method and sequential control design method.
PLC编程技术包括：经验设计法，逻辑设计法、时序图设计法、顺序控制设计法等编程方法。
Two test technologies state stable based technology and automatic test technology are given for the test of logic functions of sequential circuit.
及对时序电路逻辑功能的两种检测技术：基于状态表的测试技术和自动检测技术。
Using the programmable controller in the automobile rear axle house ring stiffener, logic sequential control was realized in the top plate automatic welding craft.
采用可编程控制器在汽车后桥壳加强环、后盖自动焊接工艺中实现逻辑顺序控制。
This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on self - adapting algorithm and USES a seventeen - valued logic model.
本文提出了一种高效的时序电路测试生成算法，该算法是建立在自适应算法的基础上，并使用了十七值逻辑模型。
A fluid logic sequential network can be classified as deterministic logic circuit and stochastic logic circuit.
流体逻辑时序线路分为确定型逻辑线路和随机型线路。
With the help of delay time, control logic accomplish the demand of sequential circuitry.
利用延迟，使控制逻辑符合时序的要求。
The logic functions of MSI counter 74161 was analysed. It could be taken as a universal sequential module to realize any synchronous sequential circuits.
分析了MSI计数器74161的逻辑功能，它作为通用的时序部件可以实现任意同步时序电路。
But fuzzy logic only pay attention to the sequential changeability of fuzzy proposition logic's value, not notice the sequential changeability of fuzzy proposition logic's conjunction operation model.
但是模糊逻辑只注意到了模糊命题逻辑真值的连续可变性，而没有认识到模糊命题连接词的运算模型的连续可变性。
VersaTiles can flexibly map the logic and sequential gates of a design.
通才可以灵活地地图的逻辑和设计顺序大门。
VersaTiles can flexibly map the logic and sequential gates of a design.
通才可以灵活地地图的逻辑和设计顺序大门。
应用推荐