This register defines the physical serial interface which will be used for data communications.
这个寄存器定义了将用于数据通信的物理串行接口。
A high speed serial data receiver, which is applied in fiber-optic communications, is presented here.
文章设计了一种用于光纤通信的高速串行数据接收芯片。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Under this background, this paper designs the system from data collection to test results representation, which includes drawing voyage chart, GPS serial port communications and user interface.
在此背景下，本文设计并实现了包括航迹图展示、GPS串口通信以及人机界面三个子系统的从数据采集到试航结果展示的完整的测试系统。
Modems used for the entire time series FPGA control, the use of DSP to CMB909 executable program control, data and images of the packaging and communications between PC machine and serial interface.
整个调制解调器采用FPGA进行时序控制，采用DSP对CMB909进行编程控制、数据帧的打包以及和PC机的串口通信。
Based PS SCM example, the detail of PC and SCM between the serial communications, data transmission and reception.
本文以PS 1016单片机为例，详细介绍了PC机与单片机之间的串行通讯、数据的发送和接收。
WIN32API communication procedures using multithreading in the form driven process for the multi-port serial communications, serial data is sent and received.
WIN32 API通讯程序采用多线程的形式进行驱动，程序中采用多串口进行通讯，有串口数据接受和发送。
Dedicated receive buffers for receiving non-data frames are provided for each port of a two-port node in a fibre-channel arbitrated-loop serial communications channel design.
专用接收缓冲区接收非数据帧的每一个端口提供两个在一个光纤端口节点通道仲裁环串行通信信道的设计。
Dedicated receive buffers for receiving non-data frames are provided for each port of a two-port node in a fibre-channel arbitrated-loop serial communications channel design.
专用接收缓冲区接收非数据帧的每一个端口提供两个在一个光纤端口节点通道仲裁环串行通信信道的设计。
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