Software pipelining is an effective approach of loop scheduling.
软件流水是循环调度的重要方法。
The generalized idea used in the previous section is called "software pipelining."
前一节中使用的思想称为 “软件管道连接（software pipelining）”。
Then a VLIW optimizing compiler adopting two-level software pipelining is described.
然后叙述采用两级软件流水的VLIW优化编译器；
This technique is called software pipelining, and this code only loses 2 cycles to stalls.
这种技术称为软件流水线(soft ware pipelining)，这段代码只损失了2个周期在暂停上。
In reverse engineering, software pipelining loop causes some difficulties in reverse translation.
在逆向工程中，软件流水循环为逆向翻译带来了困难。
The structure and allocation of the register file is a key factor affecting the performance of software pipelining.
寄存器结构及其分配是软件流水算法的关键之一。
Software pipelining is a loop optimization technique that has been widely implemented in modern optimizing compilers.
软件流水是一种循环程序的优化技术，已经广泛应用于现代优化编译器中。
Software pipelining and loop unroll are two kinds of important optimized compile technique to develop loop parallelism.
软件流水和循环展开是开发循环并行性的两种重要编译优化技术。
Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.
为了减轻存储系统影响，软件流水结合了一些存储优化技术，通过隐藏存储延迟来提高性能。
This method is completely compatible with IA-64's architecture and supports some important technology such as register rotation and software pipelining.
该方法完全兼容于ia- 64体系结构，并支持寄存器旋转和软件流水等关键技术。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
The article discuss the advantage and meaning integrating software pipelining and loop unroll in IA - 64 compiler, moreover do some deep research by experiment result.
论述了在IA-64编译器中结合使用软件流水和循环展开的优点和意义，并结合实验进行了深度探讨。
FPGA has become the first choice for designing the software radio system because of its unique advantages in distributed computing, parallel processing and pipelining.
FPGA在分布式计算、并行处理、流水线结构上有独特的优势，自然成为设计软件无线电系统的首选技术之一。
To overcome the shortcoming of low speed and low efficiency of genetic algorithm's software implementation, two hardware implementation schemes of serial and pipelining realization are put forward.
针对遗传算法软件实现速度慢、效率低的缺点，提出了便于算法实现的串行和流水线两种硬件实现方案。
In this paper we propose a de-pipelining algorithm which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart.
提出了一种反流水技术，它能够将软件流水后的优化汇编代码反向转换成语义等价的相应代码。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
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