The electric locomotive bang-bang circuit is converted into an equivalent digitalcombinational logic circuit for setting up its stuck-at fault model.
本文将机车继电器控制电路等效为数字组合逻辑电路，建立了它的固定故障等效模型。
Finally, in order to verify the feasibility of at-speed current testing, by using PSPICE software, some faults were been simulated for C432, which included open fault, stuck fault and redundant fault.
最后，为了验证全速电流测试的可行性，我们通过利用PSPICE软件对C432电路中的一些故障做了模拟，这些故障包括开路故障、固定故障和冗余故障。
Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。
Testing based on stuck-at fault model is insufficient for high performance ICs, especially for CMOS circuits.
基于固定型故障模型的测试方法已不能满足高性能集成电路，尤其是对CMOS电路的测试要求。
At present the commonly used fault models mainly consist of stuck-at fault, stuck-open fault, bridge fault, store fault, delay fault, etc.
目前常用的故障模型主要有：固定故障，开路故障，桥接故障，存储故障，时滞故障等。
At present the commonly used fault models mainly consist of stuck-at fault, stuck-open fault, bridge fault, store fault, delay fault, etc.
目前常用的故障模型主要有：固定故障，开路故障，桥接故障，存储故障，时滞故障等。
应用推荐