MyObservable starts a thread that reads the system clock.
MyObservable启动一个线程，读取系统时钟。
System clock recover is the key in digital TV system.
系统时钟恢复是数字电视系统设计中的难点。
Answer: Check the system clock on the user's computer.
答：检查用户电脑上的系统时钟。
System clock recover is the key in digital TV system.
时钟本身也是数字信号，也会干扰模拟电路。
System clock on both the CECs should be set to same date/time.
两个 CEC 上的系统时钟应该是相同的日期/时间。
Uncheck 'System clock uses UTC' and select your time zone.
取消'的系统时钟使用国际标准' ，并选择您的时区。
The accuracy is limited by the accuracy of the system clock.
其准确性受系统时钟准确性的限制。
It synchronizes your PC system clock to a network time server.
它同步您的PC系统时钟到了网络时间服务器。
The system clock controls the speed of all operations within a computer.
系统时钟控制着计算机中所有操作的速度。
External devices — For instance, Universal Serial Bus (USB) ports or the system clock.
外部设备——例如，通用串行总线(usb)端口或系统时钟。
Second, if the system clock is adjusted backwards, GENERATE_UNIQUE will return duplicate values.
第二，一旦系统时钟需要向后调整，那么GENERATE_UNIQUE将可能返回重复的值。
It will update your system clock time, synchronizing it with atomic clocks through the Internet.
该软件将更新你的系统时间，通过因特网使用原子时钟同步你的系统时间。
If so, you can solve this problem by synchronizing the users system clock with the servers clock.
如果这样，你可以通过把用户的系统时钟和服务器的时钟做同步来解决这个问题。
The system use input clock as system clock and use parallel structure in system to provide flexible speed.
全系统采用输入数据的同步时钟作为系统时钟，系统内部采用全并行的方式，以提供灵活的速度。
In clock generating circuit, we choose rc oscillation circuit as clock scheme to supply system clock source.
在时钟产生电路中，选择了RC振荡电路作为系统提供时钟源的方案。
The precision of the current UTC time's millisecond component depends on the resolution of the system clock.
当前UTC时间的毫秒组成部分的精度取决于系统时钟的分辨率。
The default time, which is retrieved from the system clock of the machine the code is running on, is used most of the time.
默认时间，即从运行代码的机器的系统时钟检索到的时间，在大部分情况下被使用。
Clock synchronization services work by changing the system clock on the client systems to match the clock on the server system.
时钟同步服务通过把客户机系统上的系统时钟改成与服务器系统相匹配的时钟而起作用。
Based on the system clock and trigger input signals, using FPGA to generate trigger output signals in given working modes.
通过FPGA实现在一定系统时钟和触发信号作用下各种工作模式的触发信号的产生。
In one form each of the successive memory cycles is a period of time of no more than a single period of the memory system clock.
在一种形式中，每个连续的存储器时钟是不大于存储器系统时钟的单个时段的时段。
For example, you might want a system clock to always return the same time so that your test has repeatable results that you can verify.
例如，您可能希望系统时钟总是返回相同的时间以便测试能够有可验证的重复结果。
To ensure accuracy, the timer should check the system clock as needed, rather than try to keep track of accumulated time internally.
若要确保精确，计时器应根据需要检查系统时钟，而不是尝试在内部跟踪所积累的时间。
This paper mainly analyzes the application of the IBIS model in the system board design and system clock design for mobile computers.
本文主要分析了IBIS模型在移动微机板参设计和在系统时钟设计中的应用。
Different components in a digital system often need different working frequencies, the way we often used is clock division from the system clock.
在数字系统中各个模块所需的时钟频率往往不相同，通常采用分频的方法由系统时钟得到所需频率。
By reading this flag, the time client knows that it is no longer connected to the network and chooses to calculate the site times from the system clock.
通过读取这个标志，timeclient就会知道它已经不再连接到网络并选择从系统时钟计算站点时间。
The paper presents a square wave modulation scheme based on TDMA signal system to resolve the problem. Also it can avoid the high speed system clock.
该文提出了一种基于TDMA信号体制下的方波调制方案，该方案既解决了远近效应，又避免了在较高的中频上采用过高的系统时钟。
If the system clock on the user's computer is ahead of the system clock on the server that contains her user profile, the server profile may not load.
如果用户电脑上的系统时钟快于含有她的用户配置文件的服务器的系统时钟，服务器的配置文件不被调用。
A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
系统时钟(371)施加到所述多个锁存器装置，使所述图案的所述推导图加载到所述多个锁存器装置中。
System clock recover is the key in digital TV system. The paper proposes a scheme of clock settlement based on buffer technology from researching DTV receiving system.
系统时钟恢复是数字电视系统设计中的难点。从研究数字电视接收系统出发，根据实际需要深入探讨并提出了一种基于缓存技术的系统时钟处理方案。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
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