The experimental results of full-adder is also presented.
在本文中给出了并行全加的实验结果。
We gave logic device of the 8bit full-adder of flow work. Introduce apple of the flow work on PLD design.
用八位全加器的工作，说明了流水线技术在PLD设计中的应用。
Many implementations of full-adder and register are contrasted and studied. The full-adder and register with the lowest power consumption are chosen.
通过对多种全加器和寄存器的实现方法进行了比较研究，选择了功耗最低的全加器和寄存器。
The circuits such as ternary full-adder, etc. designed by using this theory can have simpler circuit structures and correct logic functions. It is confirmed that this theory is efficient in...
应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能，从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器为例介绍其在数字系统设计和数字电路实验及教学中的应用。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
In this paper, we present a polarization-encoded optical full adder by using an inverse vector realized by transmissive feedback.
提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器。
A model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder (FA) fostered by the model.
提出了一种复合神经网络的算法模型，用该模型训练全加器(FA)获得了高精度分类结果。
Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.
二进制加减法，全加器实现及其性能，高速加法，带符号算术运算。
The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.
所提出的方法已用一位全加器的设计实例予以演示。
The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.
所提出的方法已用一位全加器的设计实例予以演示。
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