In 2001, Micron Technology, a semiconductor company, acquired Photobit.
在2001年，微米技术，获得Photobit半导体公司。
A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。
But on the same day, the board of Hynix, a cash-strapped memory-chip giant, shocked the markets by rejecting a proposed takeover by Micron Technology, an American competitor.
但是，就在同一天，急需现金的存储类芯片巨人Hynix公司的董事会断然拒绝了美国的一家竞争对手——美国美光科技公司——的收购建议，此举令市场大为震惊。
In deep sub - micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design.
进入深亚微米工艺后，静态功耗开始和动态功耗相抗衡，已成为低功耗设计一个不可忽视的因素。
Micron Semiconductor Technology is a key hub in Micron's network for providing support to a variety of Asia-based mobile phone and consumer electronic device manufacturers.
该处半导体制造技术研究中心则是镁光体系中负责为亚洲的智能手机及消费电子器件厂商提供技术支持的重要环节之一。
The technology is producing cells that are often only two microns thick (a micron is one-millionth of a meter).
这项技术制造的电池厚度通常仅仅是两微米(一微米是一个百万分之一米)。
For instance 'welding thickness should be 3 micron', which is a result of, should be described as: 'welding technology using 3.0a current 20 minutes to obtain 3 micron thickness'.
又比如'焊接厚度应是3微米'，这是一个结果，应该描述为：'焊接工使用3.0A电流20分钟来获得3.0微米的厚度'。
Optical rotation technology has been used in many fields as manipulating a single micron, submicron particles, and has broad prospects for development.
光致旋转技术已经在很多领域被用来作为操纵单个微米、亚微米级微粒，具有广阔的发展前景。
LOCOS is the mature technology, which is used widely for the isolation in semiconductor micron times.
硅的局域氧化工艺是一个非常成熟的工艺，在微米时代有着广泛的应用。
Sub-micron accuracy of displacement detection is obtained by adopting edge fitting technology and path matching technology.
该方法采用边界拟合和“路径匹配”技术，使位移量的检测精度达到了亚微米级。
It USES two power supplies to supply power to digital part and analog part. It USES the Hejian Technology 0.18-micron technic.
采用双电源分别为数字模块和模拟模块供电，采用和舰科技0.18微米工艺。
At present, the semiconductor devices used in the manufacturing process of etching technology, in the lab has produced sub-micron mechanical components.
目前，利用半导体器件制造过程中的蚀刻技术，在实验室中已制造出亚微米级的机械元件。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
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