The memory controller is coupled with a dynamic random access memory.
所述存储器控制器耦接一动态随机存取存储器。
A memory controller on the chip.
芯片上集成内存控制器。
Meanwhile, the design method of the memory state feedback controller is proposed.
同时，给出有记忆状态反馈控制器的设计方法。
Command data for controlling the flash memory device is input to the controller 218.
用于控制快闪存储器装置的命令数据输入到控制器218。
In addition, the integrated memory controller will support only two channel DDR-3 instead of three.
此外，整合的内存控制器将支持只有两个频道解甲还乡- 3而不是三天。
A memory controller is designed to stabilize the given system.
设计了一个“有记忆型”控制器。
At first, the memory state feedback controller is designed.
首先给出了记忆状态反馈控制器的设计方法。
At first, the memory state feedback controller is designed.
首先给出了记忆状态反馈控制器的设计方法。
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