This paper presents VISA, a scalable processor architecture based on dynamic binary translation (BT) and optimization.
本文提出一种基于动态二进制翻译优化的可扩展处理器结构VISA。
It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.
特别是流水线结构使得FFT处理器可以通过对模块级数的控制，很容易的实现不同点数的FFT计算。
It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.
特别是流水线结构使得FFT处理器可以通过对模块级数的控制，很容易的实现不同点数的FFT计算。
应用推荐