There are many resources in FPGA. There are many works about using the resources of FPGA to realize time-to-digital converter circuits.
FPGA中有着丰富的资源，目前已经有很多基于FPGA实现时间数字转换电路的研究工作。
The real time processing of high speed data flow makes strict demands on the performance of descendant digital down converter in the wideband digital receiver.
在宽带数字接收机中，高速数据流的实时处理对后继数字下变频器性能提出了极为苛刻的要求。
The principle and design method of a new design of a time-to-digital converter (TDC) implemented on an FPGA is presented.
介绍一种基于现场可编程门阵列（FPGA）的时数转换器（TDC）的原理及设计方法。
At the same time, in order to meet the need of fast measurement, pipeline analog-to-digital converter ADS800 is selected to convert analog signal of pressure.
同时，为了实现系统测量快速性的需要，选用流水线型模数转换器ads800进行压力模拟信号的数字化转换。
There exist simultaneous ion arrival and dead time effects in the time-to-digital converter, which is used in the detection system.
讨论了多个离子同时到达和死时间效应的起因和危害，并提出了有效的修正方法。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
Based on the survey of previous works, we put forward and introduce our method of realizing precise time-to-digital converter circuits by using the dedicated carry chain of FPGA.
本论文在调研了以前时间数字转换电路工作的基础上，对用FPGA中的专用进位连线来实现时间数字转换电路的研究进行了全面详细的介绍。
Finally, the paper illustrates the detailed structure of the sub-time-to-digital converter in each stage.
最后，文章还对伪流水线型时间数字转换器各级子时间数字转换器进行了优化。
However, extending the upper frequency of such function signal generator is limited by the read-out time of the memory and the conversion rate of the digital-to-analog converter.
可是，这种信号发生器的上限频率的提高受存储器的读取时间和数模转换器的转换速度的限制。为了提高数字法函数信号发生器的上限频率，我们提出了用分布存储式数字法生成函数信号。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation.
一种基于电压至时间的加窗模数转换器(adc)，可以具有可编程的基准电压、转换时间以及电压调节的精度。
Two approaches are developed:one based on a D flip-flop loop and the other based on a time-division multiplexing digital-to-analog converter (DAC).
为此提出了基于D触发器环路的相控阵信号发生技术和基于时分复用数模转换器（DAC）的相控阵信号发生技术。
Two approaches are developed:one based on a D flip-flop loop and the other based on a time-division multiplexing digital-to-analog converter (DAC).
为此提出了基于D触发器环路的相控阵信号发生技术和基于时分复用数模转换器（DAC）的相控阵信号发生技术。
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