This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability.
本文以usb逻辑分析仪作为一种典型的被测对象，进行了可测性设计的再开发工作，使其具有支持IEEE 1149.1边界扫描功能的设备结构。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
So the design of boundary scan is essential in the design of chips. IEEE instituted a standard for it, and the standard is IEEE1149.1 (that can be called as JTAG standard also).
边界扫描设计已逐渐成为芯片设计中不可或缺的部分，IEEE为其制定了相关标准，即ieee1149.1标准(也称为JTAG标准)。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
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