NRZ code doesn't contain synchronous clock frequency.
它本身不含有位同步时钟分量。
Input clock frequency of 500hz, the time for lights between 1-4 seconds, they can control.
输入时钟频率为500hz，灯亮的时间在1—4秒之间，可以自由控制。
The clock frequency is 1 MHz. The device samples sensor-read data during the write operation.
时钟频率为1兆赫。在写操作的过程中，设备从传感器独处的数据总取样。
Retriggerable mono MVBR NHZL times out at slightly longer than half of original clock frequency.
可重触发单mvbr NHZL时间稍长原始时钟频率的一半。
This will allow NVIDIA to raise the maximum clock frequency of memory from present 1800 MHz to 2200 MHz.
这将使NVIDIA的提高，最高的时钟频率的内存，从目前的1800兆赫到2200兆赫。
Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.
结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。
This makes possible to control the plural flows of data even with the considerable increase for clock frequency.
这使得能够控制复数流动的数据，甚至与相当的增加时钟频率。
Best frequency relation is given between IF coherent oscillating source and clock frequency of full coherent radar.
给出了全相参雷达频率源的中频相干振荡源及时钟频率之间的最佳频率关系。
This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
In this case, the crystal oscillator can not provide a stable clock frequency, which results in the abnormality of the device.
在这种情况下，晶体振荡器就不能为设备提供稳定的时钟频率，导致设备工作异常。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
If maximum performance is required, a crystal must be used to ensure the maximum clock frequency is approached but not exceeded.
如果需要最佳性能，必须保证晶振趋近于时钟频率，但是不能大于时钟频率。
The third counter starts counting in the first clock frequency when receiving the enabling signal, and stops counting when the enabling signal stops.
一比较器，接收上述第一计数器及上述第二计数器的计数值，以产生一致能信号输出；
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Intel Core i5 and Core i7 operates well below its thermal and electrical limits, allowing the Turbo Boost to "overclock" the CPU clock frequency and speed.
英特尔的Core i5和Corei7运行，远低于其热和电的限制，使涡轮推动的“超频”的CPU时钟频率和速度。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
Adding parallelism typically increases gate count, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.
添加并行一般通过门数增加来实现，但提高计算效率要求降低时钟频率以满足实时需求。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
Therefore, the clock frequency directly affect the speed of MCU, clocking circuit and the quality of directly influence the stability of single-chip microcomputer system.
因此，时钟频率直接影响单片机的速度，时钟电路的质量也直接影响单片机系统的稳定性。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.
随着时钟频率的不断提高，微处理器的性能受锁相环的影响越来越大，锁相环技术已经成为当代微处理器的核心技术之一。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
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