The hot carrier effects (HCE) in deep sub-micron devices has been studied.
对深亚微米器件中热载流子效应(hce)进行了研究。
With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.
伴随着深亚微米集成电路时代的来临，芯片的特征尺寸已经缩小到纳米尺度。
A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper.
介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统。
We present a novel method, used to build the I-V characteristic equations of the MOSTs in the deep sub-micron circuits.
提供了一种新的方法，用于建立深亚微米电路中MOST的伏安特性方程。
Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems.
超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
The present invention further relates to a deep sub-micron MOS integrated circuit die comprising a thick-oxide transistor-based preamplifier.
本发明还涉及一种深亚微米mos集成电路管芯，包括基于厚氧化物晶体管的前置放大器。
The thermal resistance of DSOI devices is very close to that of bulk devices and DSOI devices can keep this advantage into deep sub-micron realm.
DSOI器件的衬底热阻和体硅器件非常接近，并且在进入到深亚微米领域以后能够继续保持这一优势。
This paper presents the design and realization of a new type of video format conversion IC with LSI, deep sub-micron and analog-digital compatibility.
介绍了一种新型的超大规模、深亚微米、模数兼容的视频格式转换芯片的设计与实现。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。
This thesis first analyzes basic design of sense amplifier in deep sub-micron system, compares and discusses the mismatch problem, and then the new design is presented.
本文首先分析传统设计的问题，然后针对深亚微米系统，对失配产生的问题进行比较分析，在此基础上提出改进方法和新型结构。
Based on simulation, the characteristics and mechanisms of failure on a deep sub-micron grounded-gate NMOS (GGNMOS) are studied under TLP (transmission line pulse) stress.
对TLP(传输线脉冲)应力下深亚微米ggnmos器件的特性和失效机理进行了仿真研究。
It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.
大量的实验结果表明：与基于模拟器的方法相比，采用该系统可以快速综合出可制造的深亚微米cmos模拟单元电路。
The accurate measurements of local micro-stress and strain in ultra deep sub-micron semiconductor structures usually resort to complicated microstructure analysis, measurement methods.
超深亚微米半导体结构中的局域微应力、应变的精确测量通常必须借助复杂的微结构分析、测量手段。
This paper presented the various technologies in RF design and explored the feasibility and difficulties of deep sub micron CMOS RF design. And problems associated are also discussed.
本文介绍了当今RF设计的主流工艺，并分别对基于硅的深亚微米cmos工艺在RF设计中的可行性和困难进行了研究，评述了其中存在的问题。
In deep sub - micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design.
进入深亚微米工艺后，静态功耗开始和动态功耗相抗衡，已成为低功耗设计一个不可忽视的因素。
Deep? Sub? Micron optical lithography process is facing more and more serious challenge.
深亚微米光学光刻工艺技术目前面临着越来越严重的挑战。
Deep? Sub? Micron optical lithography process is facing more and more serious challenge.
深亚微米光学光刻工艺技术目前面临着越来越严重的挑战。
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