The circuits used are Chua 'circuit and phase lock loop.
所用的电路为蔡氏电路和锁相环电路。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
数字锁相环路（DPLL）是数字相干解调技术的核心。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
The conduction of special cable and special phase lock loop technology makes high signal more accurate;
特种的传导电缆和特殊的锁相环技术使高度信号更精准；
The electronic design is similar to the one for crystal oscillator lock loop but the parameters are different.
腔自动调谐的电路设计和晶体振荡器伺服环路类似，仅仅环路参数不同。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.
一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。
Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.
通过锁相放大技术及基准电阻补偿方法提高了测量的精度，误差在10%以内。
Digital phase lock loops are widely adapted in nowadays communication systems. However, it is difficult to design the loop parameter precisely.
数字锁相环在实际通信系统中应用广泛，但其精确的环路参数设计比较困难。
The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.
使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
The performance of synchronization tracking using pilot is analyzed, followed by a numerical method to determine the optimal lock loop parameters to minimize average bit error rate (BER).
分析了利用导频同步跟踪的性能，以及提出了一个数值方法确定最优环路参数以最小化误码率。
Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
The principle of phase lock loop and its application in the motor power-measuring system are introduced, furthermore the design and analysis of the circuit for constant speed control are provided.
介绍了摊铺机行驶控制系统的基本要求，以单边行驶回路为例探讨了其工作原理； 根据摊铺机对行驶速度的要求，分析了恒速控制技术，探讨了行驶系统控制方式。
Finally, a simulation analysis for the improved FFT frequency correction technology and phase-lock loop is maked, the result shows that the method also has a good performance in the low SNR situation.
最后分别对改进的FFT校频技术及锁相环进行了仿真分析，结果表明该方法在低信噪比下仍具有良好的性能。
The getLongest2() method is very similar, except that it obtains the lock on the Vector before starting the loop.
getLongest2()方法非常相似，除了在开始循环之前获取Vector上的锁之外。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
You can think of the active-lock attribute as a stronger version of the no-loop attribute.
可以将 active-lock属性 看作 no-loop 属性的加强版。
There is no reset to zero , which means that the synthesiser loop lock-up time will be variable.
没有复位至零，这意味着合成回路锁定时间将是可变的。
We begin our discussion with a description of an imbalance model, then analyse its effect on carrier tracking loop steady-state lock point and its effect on average BEP.
通过对调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。
We begin our discussion with a description of an imbalance OQPSK model, then analyze the effect on carrier tracking loop steady-state lock point and the effect on average BEP.
通过对OQPS K调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。
In order to make the track loop into lock quickly, the paper USES FFT spectral analysis to get fine frequency.
为了让跟踪环路快速入锁，这里还采用了FFT谱分析法对频率进行精捕。
With an unique design of transmission lock out loop, the calling collision of multi users is overcome.
由于设计了一种独特的发射互锁环，有效地解决了多个楼层同时呼梯的冲突问题。
We begin our discussion with a description of an imbalance model, then analyse its effect on carrier tracking loop steady-state lock point and I...
通过对调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。
We begin our discussion with a description of an imbalance model, then analyse its effect on carrier tracking loop steady-state lock...
通过对调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
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