The SPU queues a DMA PUT to transmit the buffer back to main memory.
SPU对DMA PUT进行排队，从而将缓冲区传输回主内存。
That's a pretty big difference because the SPE does not have direct access to main memory.
这的确是一个很大的区别，因为SPE并不直接访问主存。
The SPEs use the MFC to transfer data between the local store, main memory, and other SPEs.
SPE通过MFC在本地存储、主存和其他 SPE 间传输数据。
The SPU queues a DMA GET to pull a portion of the problem data set from main memory to a buffer.
SPU对DMA GET进行排队，从而将涉及的数据集的一部分从主内存传输到一个缓冲区。
The SPU queues a DMA GET to pull a portion of the problem data set from main memory into buffer #2.
SPU 对DMA GET 进行排队，从而将涉及的数据集的另一部分从主内存传输到二号缓冲区。
EA stands for effective address, which is a main memory address as viewed from the main PPE program.
EA表示有效地址，这是从主ppe程序中看到的主存地址。
So having plenty of main memory is directly related to getting the most out of such graphics chips.
因此有很大的内存空间就直接关系到让这类显卡发挥最大的作用。
Furthermore, compressed pages of a DB2 table space remain compressed in the DB2 buffer pool in main memory.
而且DB 2表空间的压缩页在主内存的db2缓冲池中仍保持压缩。
But the same code died horribly when someone introduced a 68030 machine with main memory starting at 0x8000000.
但是当将相同的代码移植到一台主存地址从0x8000000开始的68030机器上时，这些代码就会死掉。
Since the SPE does not have direct access to main memory, you cannot directly dereference this as a pointer.
由于SPE不能直接访问主存，所以无法直接将其作为一个指针废弃。
The log Buffer is the amount of main memory used to accumulate log records that will be written out to disk.
日志缓冲区是用于存放将要写入磁盘中的日志记录的主存量。
And remember that this memory modification will need to trickle down from L1 to L2 cache, and then to main memory.
不要忘了，这时对内存的修改需要先从L1写入l2高速缓存、然后才写入主存。
When a program writes to memory, the processor only modifies the line in the cache, but does not update main memory.
当一个程序写入存储，处理器仅仅只会修改缓存线，而不会更新主要的存储内容。
Every location in main memory is numbered with a sequential numeric address by which the memory location is referred.
主存中的每个位置都使用连续的数字地址编号，内存位置就使用这个地址来引用。
Committed pages are loaded into main memory only when the process first references them. Hence the name on-demand paging.
提交的页只有在第一次被引用时才装入主存，因此成为请求式分页。
For example, data structures and access methods are specifically optimized to work on data that is located in main memory.
比如，数据结构和访问方法专门针对位于主内存中的数据进行了优化。
For about 20 years now, CPUs have increased exponentially in speed, while main memory has weakly linearly increased in speed.
近20年来，CPU的速度呈指数式快速增长，而主内存的增长慢得多，大致是直线式的。
You can use it when the amount of data to be stored in the cache exceeds the main memory of the application server systems.
当要在缓存中存储的数据量超过应用程序服务器系统的主存时，您就可以使用此功能。
For DB2, the largest consumer of system main memory is its buffer pool, which is basically a single, large Shared memory region.
对于DB2，系统主存的最大消耗者是它的缓冲池，这个缓冲池基本上是一个单独的、较大的共享内存区域。
As the word and letters are entered, they are displayed in the CRT screen and stored in main memory of the personal computer.
当字母和单词被输入以后，它们显示在阴极射线管屏幕上，并且存储在计算机在主存中。
With a little care, most of the working set of a multiplayer online game can be pulled into the main memory of a large system.
只需稍加处理，多玩家在线游戏的大多数工作集就可以放在一个大系统的主内存中。
As a result, data is continually written and read from disk rather than from main memory, which is very detrimental to performance.
导致的结果是不断地从磁盘而非主内存读写数据，这是影响性能的重要限制因素。
After each data processing step, you set up both a PUT to transfer the data to main memory and a GET to get the next batch of data.
在每个数据处理步骤之后，设置一个PUT（将数据传输到主内存）和一个 GET（获得下一组数据）。
By allowing fast access to frequently used data, software can run much faster than if it had accessed the data from the main memory.
由于允许对频繁使用的数据进行快速存取，软件运行要比从主存储器中存取数据快得多。
A TLB miss requires accessing a page table that is stored in the main memory, which consumes considerably more processor cycles.
如果TLB没有命中，那么就需要访问存储在主存中的页表，而这样做需要消耗相当多的处理器周期。
The cache is generally allowed to write variables back to main memory in a different order than they were written by the program.
通常允许缓存以与程序写入变量时所不相同的次序把变量存入主存。
Because data is replicated across the cluster, each server in the cluster has enough main memory to store the entire context data.
由于数据在整个集群中进行复制，集群中的每个服务器都有足够的主存来存储整个上下文数据。
Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).
由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。
Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).
由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。
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