A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
提出了一种全新的电荷泵锁相环的行为级建模方法。
In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
In phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.
相位相干通信系统中，通常采用锁相环路来产生相干参考信号。
According to the theory of phase-locked loop, we use reflected photoelectric sensor to carry out the color recognition.
根据锁相环的原理，使用反射式光电传感器实现了系统的颜色识别。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
The software phase-locked loop (SPLL) technology in the steady speed control of permanent magnet brushless DC motor (BLDCM) in gyro was discussed.
研究了软件锁相环技术在陀螺用无位置传感器无刷直流电机稳速控制系统中的应用。
The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).
描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。
This article presents a new design structure of variable bandwidth phase-locked loop based on improving phase-locked loop of actively mode-locked fiber laser.
对主动锁模光纤激光器的锁相环进行改进，提出一种新型的“变带宽锁相环”的设计结构。
Unlike previous researches, the nonlinear analysis on the effects of delay-difference module employed in the delay phase-locked loop (DPLL)is particularly presented.
与以往研究不同，针对延迟锁相线性化环路的延迟差分环节，着重分析了其非线性特性对环路性能的影响。
This paper presents a simple tracking filter circuit, which is applicable to Doppler radar sets and consists mainly of a switched bandpass filter and a phase-locked loop.
本文提出一种简单的跟踪滤波器电路，该电路可用于多普勒雷达，主要由开关式带通滤波器和锁相环组成。
Signal demodulation of automatic block with audio frequency shift modulated track circuits was implemented with phase-locked loop (PLL) technique and a singe chip microcomputer.
利用锁相环(LL)窄带跟踪特性，与单片机结合，实现自动闭塞系统移频信号解调。
The simulation results prove that the three-phase phase-locked loop can work well in disturbance situation and variable frequency system when the frequency of the inputs is variable.
并对相位突变和频率突变的情况进行了仿真研究，说明在相位和频率发生变动时三相锁相环仍能有效地锁定相位，能够满足系统变频的要求。
In this paper we introduce the developmental phase and experimental equipments of long time delay phase-locked loop and also give the field test results via the satellite "Symphonic".
本文叙述了长延时锁相环的研制情况和实验设备，同时也给出了通过“交响乐”卫星的现场试验结果。
It USES a high precision digital phase-locked loop (PLL) to accurately recover the Synchronous reference information of raw cloud-cover image data collected by the geostationary satellite.
它用高精度数字锁相环，精确地恢复地球同步气象卫星采集的原始云图数据的同步基准信息。
Introduces the basic principle of phase-locked loop and NE564 PLL circuit structure and properties, and the use of phase-locked NE564 demodulating circuit and phase-locked frequency circuit.
介绍了锁相环的基本原理和锁相环ne564的电路结构和性能，及其用ne564构成的锁相解调电路和锁相倍频电路。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
In this paper, Experimental circuit and results of sampled phase-locked loop system that exhibit chaotic behavior are given. Experimental results are discussed, we obtained some active conclusions.
本文给出了文献产生混沌的采样锁相环系统的实验线路及实验结果，通过对实验结果进行讨论，得出一些设计采样锁相环系统的准则。
Because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.
由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
The controller make up of TMS320F2812 DSP chip, detecting circuits include sampling circuit, modulate circuit and phase locked loop and other periphery control and drive circuit.
本文设计的控制器以TMS320F2812DSP芯片为核心，加上检测电路（包括采样电路、调理电路、锁相环等）和其它外围控制和驱动电路构成。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
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