• The generalized idea used in the previous section is called "software pipelining."

    使用思想称为软件管道连接(software pipelining)”。

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  • Then a VLIW optimizing compiler adopting two-level software pipelining is described.

    然后叙述采用两级软件流水VLIW优化编译器

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  • This technique is called software pipelining, and this code only loses 2 cycles to stalls.

    这种技术称为软件流水线(soft ware pipelining),段代码损失了2个周期在暂停上。

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  • In reverse engineering, software pipelining loop causes some difficulties in reverse translation.

    逆向工程中,软件流水循环为逆向翻译带来困难

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  • The structure and allocation of the register file is a key factor affecting the performance of software pipelining.

    寄存器结构及其分配软件流水算法关键之一。

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  • Software pipelining is a loop optimization technique that has been widely implemented in modern optimizing compilers.

    软件流水一种循环程序优化技术已经广泛应用于现代优化编译器中。

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  • Software pipelining and loop unroll are two kinds of important optimized compile technique to develop loop parallelism.

    软件流水循环展开开发循环并行性重要编译优化技术

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  • Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.

    为了减轻存储系统影响,软件流水结合一些存储优化技术通过隐藏存储延迟提高性能

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  • This method is completely compatible with IA-64's architecture and supports some important technology such as register rotation and software pipelining.

    方法完全兼容于ia- 64体系结构支持寄存器旋转软件流水关键技术

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  • Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.

    软件流水一种开发循环程序指令并行技术通过并行执行连续多个迭代来加快循环的执行速度。

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  • The article discuss the advantage and meaning integrating software pipelining and loop unroll in IA - 64 compiler, moreover do some deep research by experiment result.

    论述IA-64编译器结合使用软件流水循环展开优点意义结合实验进行了深度探讨。

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  • FPGA has become the first choice for designing the software radio system because of its unique advantages in distributed computing, parallel processing and pipelining.

    FPGA分布式计算并行处理流水线结构上独特优势,自然成为设计软件无线电系统首选技术之一。

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  • To overcome the shortcoming of low speed and low efficiency of genetic algorithm's software implementation, two hardware implementation schemes of serial and pipelining realization are put forward.

    针对遗传算法软件实现速度慢效率缺点提出了便于算法实现串行流水线两种硬件实现方案

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  • In this paper we propose a de-pipelining algorithm which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart.

    提出种反流水技术,能够将软件流水优化汇编代码反向转换成语义等价相应代码。

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  • To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.

    同时为了降低FPGA资源占用,RSA算法采用流水线方式实现脉动阵列通过软硬件协同合作完成算法中素数的判定生成算法参数

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  • To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.

    同时为了降低FPGA资源占用,RSA算法采用流水线方式实现脉动阵列通过软硬件协同合作完成算法中素数的判定生成算法参数

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