The proposed method doesn't need hardware synchronization circuit and can perform the calculation of fundamental positive sequence component of the supply voltage in real time.
这种方法不需要硬件同步电路，能实时地计算电源电压中的基波正序分量。
This circuit is implemented on a monolithic chip, which is comprised of a period time sampling unit, a peri-od distanee preset unit, an arithmetic unit, a clock and time sequence unit.
电路主要由周期计时电路、周期数据预置电路、运算电路及时钟和时序等电路构成。
S7-200 series PLC of SIEMENS company is used in order to achieve the aim of controlling the time-sequence, precision and charge circuit.
用当前占主流地位的西门子s7- 200系列PLC进行编程，实现合成回路动作过程的时序控制、精度控制以及充电电路的控制等。
An improvement of logic design approach for time-sequence control circuit is presented.
本文提出了逻辑法设计时序控制电路的改进方法。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Logical control circuit is implemented by CPLD, and its main function is the whole units time sequence and logical control.
逻辑控制电路由CPLD完成，主要完成整个处理单元的时序和逻辑控制。
A method of separating the TIP data from the HRPT is proposed. The design idea, part of the circuit, time sequence and programming flow diagram are given.
介绍一种从HRPT中分离tip数据的方法，并给出设计思想，部分电路、时序及程序流程图。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
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