A brief survey is given to the new advances of MPEG-2 video decoder chips.
本文简要介绍应用前景广阔的MPEG - 2视频解码芯片的新进展。
The management of the bitstream and the parsing of video data are the basis of the video decoder.
网络视频解码的基础是码流的管理和视频流的解析。
The input bit rate and the output frame rate of video decoder is fix, so a Rate Buffer is needed to balance this rate difference.
而经解码后显示的侦速率是恒定的，这就要求在解码端有一个缓冲器来实现输入码率与输出码率间的过渡。
By using the full functional video decoder and cooperated with the DSP program, this system can be compliant with various video formats.
通过采用功能全面的视频解码器并辅以dsp软件的配合，本系统可以兼容多种视频格式。
The invention provides an image processing platform, which comprises a video decoder used for converting input simulation video images into digital video images;
本发明提供一种图像处理平台，其包括：一视频解码芯片，用于将输 入的模拟视频图像转化为数字视频图像；
The product of the company includes frequency of silicon tuner, demodulator, MPEG and video decoder, and dial in the light of what mothball channel applies modem.
公司的产物包括硅调谐器、解调器、MPEG 音频和视频解码器，以及针对后备频道应用的拨号调制解调器。
This system absorbs image by CCD, passes again after video decoder handles the vehicle identification judgement that carries out image to vehicle identification system.
该系统由CCD摄取图像，经视频解码器处理后再传给车辆识别系统进行图像的车辆识别判断。
It USES the PCI interface chip SAA7146A special for media processing produced by Philips, and connects simply with video encoder, video decoder, audio encoder and decoder.
设计选用PCI多媒体接口芯片SAA7146A，方便的实现了与视频编码器、视频解码器和音频编解码器的连接。
IIC bus protocol analysis on the basis of a detailed description in the text adopted by the IIC module DM642 video decoder chip register configuration, calibration process.
在分析IIC总线协议的基础上，文中详细叙述了DM 642通过IIC模块对视频编解码芯片的寄存器进行配置、校验的流程。
It supports most CMOS image sensors in the market as well as video decoder controllers that are able to provide 30 frames of uncompressed video data per second at VGA resolution.
它支持市场上大部分COMS图像传感器，以及视频解码器控制器，并能够提供每秒30帧的未压缩的视频数据。
An implementation method and the implementation result of HDTV video decoder bit stream distribution circuit are given out in this paper based on the HDTV video stream construction.
文中在介绍高清晰度电视视频码流结构的基础上，提出了高清晰度电视视频解码器中码流分配电路的实现方法，并给出了实现结果。
This research is very important for implementing a HDTV video decoder by using general purpose DSP. It promotes the development of DSP usage in consumer electronic application field.
这项研究对使用通用DSP实现高清晰度电视视频解码乃至实现整个信源解码器有重要的价值，推动了通用DSP在消费电子领域多媒体技术方面的应用。
Last month, graphics chip maker ATI Technologies Inc. unveiled a processor that incorporates a high-quality video decoder as well as other technology typically found in high-end TVs.
上个月，AT I公司发布了整合高清晰视频解码以及其他高端电视具备的技术指标的处理器。
The architecture of video decoder is transforming from dedicated hardware to HW/SW partition owing to the powerful process of hardware and the flexibility and programmability of software.
视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。
Later this paper implements the software of modified video encoder and decoder of MPEG-4 using VC on PC platform, which verifies feasibility of modified algorithms.
随后，本文在PC机上采用VC编写了改进后的MPEG - 4视频编码器和解码器的软件，验证了对算法改进的可行性。
The building block of it is the digital television decoder core, which decodes the video and audio signal.
解码内核是其完成视频和音频信号解码功能的基本部件。
In distributed video coding (DVC) because the decoder cannot have access to the current frame, modeling the temporal correlation noise becomes a difficult task.
在分布式视频编码(DVC)中，由于解码端不能获取当前编码帧的信息，精确地对时域相关噪声进行建模变得更为困难。
With weighting the factors of video subjective quality, it integrates the technology of transmission, robust coding and error resilience of the decoder.
该方法是在权衡考虑影响视频主观质量多种因素的基础上，并综合了传输、鲁棒性编码和解码端错误隐藏等技术的抗误码方法。
ST Application programming Interface-STAPI drives the underlying hardware, video and audio decoder and display devices, and provides the upper software easy programming interface.
ST应用程序接口-STAPI负责底层硬件视音频解码和显示的驱动，并向上层软件提供良好的编程接口。
An error concealment algorithm is proposed as a post-processing tool at the decoder side, with the aim of recovering the motion vectors and image blocks lost during the video sequence transmission.
提出了一种误差掩盖算法，作为在解码器端的后处理工具，以恢复视频序列在传输过程中丢失的运动矢量和图像块。
A video interface design based on XCV300FPGA is introduced. The implementations of video-in decoder and memory DAC video-out are discussed in detail.
介绍了一种以xcv300 FPGA为核心的视频接口设计。同时按照视频输入、解码存储、DAC转换输出视频流的流动顺序，给出了实现方法。
In another aspect, for a first interlaced scanning video frame in a video sequence, a decoder decodes a bitplane signaled at frame layer for the first interlaced video frame.
另一方面，对于视频序列中的第一隔行扫描视频帧，解码器解码第一隔行扫描视频帧的帧层处用信号表示的位平面。
Decoder: a device used to unscramble data signals and display them on a video screen.
译码器：解读数据信号并把它列出于显示器的荧光屏上的装置。
In this article, we mainly discussed its applications on video capture, controllable delay line and MPEG-2 decoder.
本文着重讨论了其在视频采集，可控延时线和MPEG- 2解压等方面的应用。
In this article, we mainly discussed its applications on video capture, controllable delay line and MPEG-2 decoder.
本文着重讨论了其在视频采集，可控延时线和MPEG- 2解压等方面的应用。
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