深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
伴随着深亚微米集成电路时代的来临，芯片的特征尺寸已经缩小到纳米尺度。
With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
集成电路器件的特征尺寸进入深亚微米时代后，由于微细化和性能方面的影响，一些传统的器件结构将不再适用。
With the IC scaling down to deep-sub micro generation, due to the degradation of performance, any conventional device structure is not applicable to IC.
衬底噪声耦合是深亚微米混合信号集成电路中常见的噪声干扰效应，严重地影响了模拟电路的性能。
Substrate noise coupling effect often occurs in the DSM mixed signal ICs, which seriously interferes the normal performance of the analog circuits.
成功地将共面线应用在深亚微米高速集成电路的设计中，并给出了放大器芯片和共面线的测试结果。
Finally, the coplanar stripline on-chip is successfully used in the design of the high-speed IC's, and some measured results are also given.
光刻校正技术已成为超深亚微米下集成电路设计和制造中关键的技术。
The optical lithography correction techniques become key technologies in the IC designing and manufacturing of VDSM.
综述了亚微米、深亚微米干法刻蚀和相关技术的最新进展及其在超大规模集成电路制造中的应用。
The latest advance of the dry etching for submicron fabrication in ULSI production and interrelated technology are introduced.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
模拟电路数字化虽可解决很多深亚微米工艺射频模拟集成电路设计中出现的问题，但暂时依然无法完全替代传统模拟电路器件和结构。
Though it can solve many problems during RF analog IC design in deep submicron meter technology, but it still can't i(?)place all conventional analog circuit component or structure.
随着集成电路设计进入超深亚微米阶段，电路复杂度不断提高，芯片测试面临着巨大的挑战。
As the integrated circuit design has stepped into the deep ultra-submicron stage, the complexity of the circuit increases continually, chip test faces very huge challenge.
该试验方法简便、可靠，适用于亚微米和深亚微米超大规模集成电路的可靠性评价。
This method is convenient and reliable in use. It is suitable for the reliability evaluation of sub-micrometer and deep sub-micrometer VLSI.
本发明还涉及一种深亚微米mos集成电路管芯，包括基于厚氧化物晶体管的前置放大器。
The present invention further relates to a deep sub-micron MOS integrated circuit die comprising a thick-oxide transistor-based preamplifier.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
本文提出的深亚微米下微处理器的物理设计流程，对当前集成电路的物理设计具有普遍意义。
The DSM physical design flow proposed in the dissertation is suitable and meaningful for general IC design.
本文提出的深亚微米下微处理器的物理设计流程，对当前集成电路的物理设计具有普遍意义。
The DSM physical design flow proposed in the dissertation is suitable and meaningful for general IC design.
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