数字锁相环路(DPLL)是数字相干解调技术的核心。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
本文分析了数字锁相环路的寄生频偏,它是现代通讯系统中频率合成器的重要指标之一。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏,它是现代通讯系统中频率合成器的重要指标之一。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
应用推荐