熟悉深亚微米工艺设计规则。
本文综述了深亚微米光刻和纳米光刻技术。
In this article, deep submicron lithography and nano processing are reviewed.
深亚微米芯片设计的会带来许多新的挑战。
随着深亚微米技术，串扰噪声问题越来越严重。
With deep submicron technology, crosstalk noise becomes more and more serious.
对深亚微米器件中热载流子效应(hce)进行了研究。
The hot carrier effects (HCE) in deep sub-micron devices has been studied.
深亚微米光学光刻工艺技术目前面临着越来越严重的挑战。
Deep? Sub? Micron optical lithography process is facing more and more serious challenge.
介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统。
A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper.
本文针对超深亚微米通用微处理器中的多级tlb设计开展研究。
This research focuses on multi level set associative TLB performance of the general purpose microprocessor.
本文从器件物理、器件结构和工艺等三个方面介绍了深亚微米器件。
The physics, structure and technology of the deep submicron MOS devices were given.
随着深亚微米工艺的广泛应用，瞬态故障已成为芯片失效的主要原因。
Since deep submicron manufacturing process is widely used in microprocessors, transient faults have become the main source of chip faults.
分析了深亚微米技术对IDDQ测试的影响以及IDDQ的改进方法。
Then, the influence of deep-submicron technology on IDDQ testing is explained. And the improved IDDQ testing methods are also given.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
光刻校正技术已成为超深亚微米下集成电路设计和制造中关键的技术。
The optical lithography correction techniques become key technologies in the IC designing and manufacturing of VDSM.
提供了一种新的方法，用于建立深亚微米电路中MOST的伏安特性方程。
We present a novel method, used to build the I-V characteristic equations of the MOSTs in the deep sub-micron circuits.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
伴随着深亚微米集成电路时代的来临，芯片的特征尺寸已经缩小到纳米尺度。
With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.
超深亚微米ic设计中互连线的串扰情况与详细布线方案和信号波形密切相关。
In IC design under VDSM technology, the crosstalk situation of interconnecting is related nearly with the scheme of detailed routing and the waveforms of signals.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。
Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems.
该试验方法简便、可靠，适用于亚微米和深亚微米超大规模集成电路的可靠性评价。
This method is convenient and reliable in use. It is suitable for the reliability evaluation of sub-micrometer and deep sub-micrometer VLSI.
介绍了一种新型的超大规模、深亚微米、模数兼容的视频格式转换芯片的设计与实现。
This paper presents the design and realization of a new type of video format conversion IC with LSI, deep sub-micron and analog-digital compatibility.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
大的负载电容和日益严重的线间耦合使得深亚微米总线面临着功耗、延迟和可靠性等问题。
Due to the large load capacitance and increasingly serious inter-wire coupling, deep submicron buses are facing many problems like power, delay and reliability.
本发明还涉及一种深亚微米mos集成电路管芯，包括基于厚氧化物晶体管的前置放大器。
The present invention further relates to a deep sub-micron MOS integrated circuit die comprising a thick-oxide transistor-based preamplifier.
针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。
A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
随着集成电路设计进入超深亚微米阶段，电路复杂度不断提高，芯片测试面临着巨大的挑战。
As the integrated circuit design has stepped into the deep ultra-submicron stage, the complexity of the circuit increases continually, chip test faces very huge challenge.
对TLP(传输线脉冲)应力下深亚微米ggnmos器件的特性和失效机理进行了仿真研究。
Based on simulation, the characteristics and mechanisms of failure on a deep sub-micron grounded-gate NMOS (GGNMOS) are studied under TLP (transmission line pulse) stress.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
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