The design method of LED big screen scanning circuit is introduced, and the virtues of programmable logic device application on high-speed digital system are presented.
介绍了LED大屏幕扫描电路的设计方法，阐述了可编程逻辑器件在高速数字系统应用中的优点。
The digital logic chip of the invention and the method of design for testing can realize the observation of circuit scanning test by adopting few pins.
本发明的数字逻辑芯片及其可测试设计的方法，能够通过少量管脚实现电路在扫描测试时的可观测。
The practice shows that this method can save a lot of FPGA resources, which just need over 100 LE logic unit to effectively solve the FIR digital filter design algorithms in FPGA resource issues.
实践表明，此方法可以节省大量的FPGA资源，仅仅需要100多个LE逻辑单元，就可以有效解决FIR数字滤波器算法在FPGA设计中资源紧张的问题。
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