深亚微米集成电路：通常把0.35-0.8μm及其以下称为亚微米级，0.25um及其以下称为深亚微米，0.05um及其以下称为纳米级。深亚微米制造的关键技术主要包括紫外光刻技术、等离子体刻蚀技术、离子注入技术、铜互连技术（不是同互连）等。国际上集成电路的主流生产工艺技术为0.010μm-0.028μm。
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
伴随着深亚微米集成电路时代的来临，芯片的特征尺寸已经缩小到纳米尺度。
With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
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