该结构并行效率高，并可达到线性加速比。
It is shown that the architecture has a high efficiency for parallel processing and a nearly linear speed-up.
得到线性加速比，并行效率达到90%以上。
The liner speedups have been obtained, and the parallel implementation efficiency preponderates over 90%.
实验证明，这种并行模型能够得到较高的线性加速比。
Experiments prove that this model can get higher linear speedup.
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