闩锁效应（Latch-up）是CMOS集成电路中一个重要的问题，这种问题会导致芯片功能的混乱或者电路直接无法工作甚至烧毁。
比如，在大多数情况下，IC闩锁效应(latch-up)是由布局引起的，应当通过设计规则来避免。信号和电源引脚上的负电压可能会导致HVIC故障及损坏，从而毁掉整个变频器系统。
基于535个网页-相关网页
...的方面是发音和拼写 » The other two languages two different aspects of pronunciation and spelling 闩锁效应 » Lock effect 你2了? » You 2?
基于1个网页-相关网页
有关闩锁效应 latchup or latch-up
Latch-up effect is one of main cause that CMOS IC becomes invalid in application,and as device channel length becomes smaller and smaller,Latch-up effect in CMOS structure is stand out increasingly.
闩锁效应是CMOS集成电路在实际应用中失效的主要原因之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。
参考来源 - CMOS集成电路闩锁效应抑制技术·2,447,543篇论文数据，部分数据来源于NoteExpress
同时，为了防止闩锁效应的产生，在电路的大尺寸数字输出反相器的PMOS管和NMOS管的周围增加了保护环。
At the same time, to prevent the generation of latch-up, guard rings are added around the large dimension digital output inverter PMOS and NMOS transistors of the circuits.
本文采用较全面的包括四个寄生双极晶体管和MOS管的闩锁模型，详细分析了瞬态辐照下CMOS反相器的闩锁效应。
In this paper, a new lumped elements latchup model consisting of four bipolar transistors is used to analyze the latchup effect of CMOS inverters in transient radiation environment.
此外，本文在版图方面进行了研究，对匹配、串扰、噪声、寄生效应、闩锁效应和天线效应分别进行了论述，给出相应的解决办法。
Besides, layout is researched in-depth. Discussing the matching, crosstalk, noise, parasitic effects, the latch and antenna effect, I give appropriate solutions.
应用推荐