In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
The thesis presents the design and realization of a data synchronous acquisition system in integrated protection based on FPGA and digital frequency multiplying technique.
本论文的任务是设计并实现基于FPGA及数字倍频技术的集成保护中数据同步采集系统。
Complex Programmable Logic Device (CPLD) is one of Application Specific Integrated Circuit (ASIC) that has been widely used, especially adapt to design digital system.
复杂可编程逻辑器件(CPLD)是目前应用最为广泛的可编程专用集成电路(ASIC)之一，特别适合于数字系统的设计和开发。
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