FIFO memory buffer FIFO缓冲存储器
fifo-memory fifo存储器
FIFO virtual memory 先进先出虚记忆器
fifo buffer memory fifo缓冲存储
virtual memory FIFO 先进先出虚记忆器
dual port fifo buffer memory 双端口fifo缓冲存储
In this paper, we discuss a FIFO memory electrocircuit, which is designed from the top down and have been fabricated successfully.
文中的设计思想和具体的逻辑电路可以通用于所有先进先出存储器的设计。
The system controls the logic of the data acquisition board by programmable logic device (PLD) with the center of the ARM microcontroller and FIFO memory and provides the simulate waveforms.
系统以ARM微处理器和FIFO存储器为核心，利用可编程逻辑器件实现对整个底层数据采集系统的逻辑控制，并给出了时序控制部分的仿真波形。
The new method improves the efficiency of bus and reduces the size of frame buffer in memory and FIFO in DMA channel.
这种结构提高了总线效率，并且减小了内存中解码帧缓冲器和通道中FIFO的面积。
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